One of great features is the memory controller integration into the silicon die that is believed to be able to boost the whole system performance significantly. An onboard memory controller will improve the memory access latency as compared to traditional memory access through dedicated bus interface. If you are aware, current AMD core architecture such as K8 already has memory controller being integrated on the silicon level.

Besides this, Nehalem is supported by a high speed internal bus known as Quick Path Interconnect. It will replace current FSB (Front Side Bus) in most of the current design. Again, the concept is quite similar to existing HyperTransport technology available in current AMD silicon. Of course they are differences in terms of technology and protocol involved to make them more powerful since Intel is always in leading position with clear roadmap and advanced process technology. On top of these, some of the new features which will be implemented in this silicon are multiple cores with new HT (Hyper-threading) technology, 8MB sharable L3 cache size as well as DDR3 memory support.


Intel® microarchitecture codename Nehalem, offers the latest in processor innovation, including:

Dynamic scalability, managed cores, threads, cache, interfaces, and power for energy-efficient performance on-demand.

• Design and performance scalability for servers, workstations, notebooks, and desktops with support for 2-8+ cores and up to 16+ threads with Intel® Hyper-Threading Technology (Intel® HT Technology), and scalable cache sizes, system interconnects, and integrated memory controllers.
• Intelligent performance on-demand with Intel® Turbo Boost Technology taking advantage of the processor's power and thermal headroom. This enables increased performance of both multi-threaded and single-threaded workloads.
• Increased performance on highly-threaded applications with Intel HT Technology, bringing high-performance applications into mainstream computing with 1-16+ threads optimized for new generation multi-core processor architecture.
• Scalable shared memory features memory distributed to each processor with integrated memory controllers and Intel QuickPath Technology high-speed point-to-point interconnects to unleash the performance of future versions of next-generation Intel® multi-core processors.
• Multi-level shared cache improves performance and efficiency by reducing latency to frequently used data.